standard9755
04-23-2011, 01:49 PM
hi,Microsoft Office 2007 Ultimate (http://www.office2010productkey.us/office-2007-key),
we are interfacing coldfire mcf5232 processor which has a fpga. processor accesses fpga registers using standard study create cycles (with no burst).
these read/write cycles are terminating centered on transnfer acknowledge signal. fpga is generating this signal when it's ready to write/ read the information.
we could read/write data when processor system clock is configured to 75mhz and 100 mhz. but it is not working when processor system clock is 150mhz.
we followed below mentioned steps to debug this issue.
step1 :
checked fpga input clock,Office 2007 Ultimate (http://www.office2010-key.eu/office-2007-key), processor clkout frequency on board. – all are correct.
processor clock clkout frequency
75mhz 37.5mhz
100mhz 50.0mhz
150mhz 75.0mhz
step2 :
we checked processor cycles termination register configuration to external termination is set. cscr5.8 (aa - auto acknowledge enable is 0)
step3 :
we configure system clock to 75mhz, we could create and read knowledge in fpga registers. processor write cycle is terminating after sampling “transfer acknowledge” signal. – as expected
step4 :
we configure system clock to 100mhz,Office 2010 Activation Key (http://www.office2010productkey.us/), we could write and go through information in fpga registers. processor compose cycle is terminating after sampling “transfer acknowledge” signal. – as expected
step5 :
we configure system clock to 150mhz,Office Pro 2010 Key (http://www.office2010-key.eu/), we saw in fpga integrated logic analyzer,Windows 7 Ultimate (http://www.key-windows-7.de/), processor chip select is going high before “transfer acknowledge” signal changing to low. can you please advise us why processor chip select is going high (termination of cycle) before sampling “transfer acknowledge” low.
step6 :
to check above misbehavior we tied fpga “transfer acknowledge” signal to permanently high and checked processor chip select behavior in integrated logic analyzer during processor write cycle .
for 75mhz and 100 mhz - we saw chip select signal is continuously low and not going high for 29 cycles.
for 150 mhz - even though transfer acknowledge signal is permanently high. chip select signal is going low and after 4 cycles it can be going high.
thanks in advance.
we are interfacing coldfire mcf5232 processor which has a fpga. processor accesses fpga registers using standard study create cycles (with no burst).
these read/write cycles are terminating centered on transnfer acknowledge signal. fpga is generating this signal when it's ready to write/ read the information.
we could read/write data when processor system clock is configured to 75mhz and 100 mhz. but it is not working when processor system clock is 150mhz.
we followed below mentioned steps to debug this issue.
step1 :
checked fpga input clock,Office 2007 Ultimate (http://www.office2010-key.eu/office-2007-key), processor clkout frequency on board. – all are correct.
processor clock clkout frequency
75mhz 37.5mhz
100mhz 50.0mhz
150mhz 75.0mhz
step2 :
we checked processor cycles termination register configuration to external termination is set. cscr5.8 (aa - auto acknowledge enable is 0)
step3 :
we configure system clock to 75mhz, we could create and read knowledge in fpga registers. processor write cycle is terminating after sampling “transfer acknowledge” signal. – as expected
step4 :
we configure system clock to 100mhz,Office 2010 Activation Key (http://www.office2010productkey.us/), we could write and go through information in fpga registers. processor compose cycle is terminating after sampling “transfer acknowledge” signal. – as expected
step5 :
we configure system clock to 150mhz,Office Pro 2010 Key (http://www.office2010-key.eu/), we saw in fpga integrated logic analyzer,Windows 7 Ultimate (http://www.key-windows-7.de/), processor chip select is going high before “transfer acknowledge” signal changing to low. can you please advise us why processor chip select is going high (termination of cycle) before sampling “transfer acknowledge” low.
step6 :
to check above misbehavior we tied fpga “transfer acknowledge” signal to permanently high and checked processor chip select behavior in integrated logic analyzer during processor write cycle .
for 75mhz and 100 mhz - we saw chip select signal is continuously low and not going high for 29 cycles.
for 150 mhz - even though transfer acknowledge signal is permanently high. chip select signal is going low and after 4 cycles it can be going high.
thanks in advance.